Most semiconductors, including all DRAMS, include capacitors. For example, a 16 Meg DRAM includes over 16 million capacitors each. For the purpose of storing individual bits of information, these capacitors are accessed by connections through access transistors and sense amps, connected through a periphery circuit.
CMOS technology, with low static power consumption and high speed, has become the technology of choice for almost all VLSI applications. Because it employs both p-channel and N-channel MOS transistors, parasitic NPN and PNP bipolar transistors are formed. Together they form the PNPN layer which is commonly known as the silicon-controlled rectifier (SCR); they stay on once they have been turned on. This mode is known as "latchup" and can be self-destructive because excessive currents can flow through the junctions. The reduction in dimensions further accentuates this parasitic component responsible for a self-destructive mode.
In order to model latchup, it is convenient to use the four-layer configuration as two coupled transistors, shown in FIGS. 1. As illustrated in FIG. 1A, a p+ source/drain and a p substrate form the emitter and collector regions of a vertical PNP transistor, schematically shown as Q1. An n+ source/drain and an n-well form a lateral NPN transistor, schematically shown as Q2. The parasitic vertical PNP and lateral NPN bipolar transistors Q1, Q2 can introduce latchup if either of the base-emitter junctions becomes forward biased. The parasitics can be described as a four layer P+NPN+ diode called a silicon-controlled rectifier (SCR). The SCR's operation depends on an internal feedback mechanism triggered by operating voltage above VCC or below ground; by internal thresholds; by radiation-induced currents; or by photo excitation.
A p-channel device will latchup when its source or drain is forced above VCC with a charge current, called the trigger current. This current causes Q1 to become forward biased and to turn on. Referring to FIG. 1B, Q1's collector current, ICI, now feeds with the base of Q2 (IB2) and the parasitic resistor R2. Since R2 pulls base current from Q2, it causes a voltage to appear at Q2's base. When this potential reaches the range of 0.6 to 0.7 volts (1NPN.times.R2), Q2 turns on and begins to feed current into R1 and Q1's base. This latchup loop will continue until voltage is removed or the circuit self destructs.
An n-channel device will latchup when its source or drain voltage is forced below V.sub.SS and a similar process begins at Q2. The current required to initiate latchup can be expressed in terms of the fundamental transistor parameter alpha (.alpha.). The variation of alpha is a fundamental feature of the SCR.
U.S. Patent application Ser. No. 07/200,673 describes a semiconductor circuit device in which border areas, including perimeter border areas and intermediate border areas, are capacitors. The filter capacitors are in electrical communication with lead frame connection pads, to which the lead frame connection wires are attached. This establishes a filter capacitance in excess of 0.001 .mu.F on the semiconductor device side of the lead frame connection wires, thereby filtering voltage transients which may be generated by the lead frame connection wires.
Latchup can occur in a capacitor as a result of a short from gate to substrate. The short may be due to gate--oxide breakdown in the field over time.
In order to reduce latchup, it is possible to form the capacitor with a barrier to substrate. This forms a depletion mode capacitor. A depletion mode capacitor has a top plate (sometimes called a gate) over a depletion region of the substrate or bottom plate. The depletion region is so-called because there is a depletion of mobile carriers (electrons or holes). Charge is uncovered across the depletion, and the resulting field rapidly sweeps any charge which enters into the depletion region across the region.
The result of the depletion region in the capacitor is that the capacitor accepts charge at low voltage and has equal depletion depths across the capacitor. More importantly, the capacitor is less likely to cause latchup.
FIGS. 2 show the formation of a barrier layer under the capacitor in the left side of the drawings. A depletion region 2 is implanted through isolation oxide 3, followed by deposition of gate polysilicon 4. Active areas 5 are then implanted. On the right side, no barrier is implanted under the gate poly 4, but active areas 6 are implanted. The depletion region normally requires a separate mask step and implant step.